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Check GitHub profileBooting coreboot on Intel Comet Lake S RVP8
Published at August 31, 2020 · 10 min read
This blog post shows the procedure of building coreboot for a Comet Lake S platform. Also it describes problems occurred when building and booting the image. As a bonus, few tips and tricks will be shown how to fix/workaround these kind of problems....
Dell OptiPlex and coreboot - a story about porting cursed hardware (part 1)
Published at June 24, 2020 · 7 min read
This post begins a new series telling a story of a stubborn firmware engineer who overcame never-ending amount of obstacles to create a Dell OptiPlex 9010 workstation as open as possible. In this series, you will not only read about the adventures which accompanied the work on the hardware but also you will have a chance to learn the way of BIOS developer....
Categories: firmware
Installing TrenchBoot in UEFI environments
Published at May 6, 2020 · 17 min read
This blog post will show you how to install NixOS on UEFI platforms and how to install TrenchBoot on them....
Categories: firmware os-dev security
User friendly tutorial for enabling HTTPS support in iPXE
Published at May 6, 2020 · 5 min read
This article will show you how to replace old HTTP with much safer HTTPS when booting platforms/computers over network. You will read how to quickly incorporate open-source network booting solution based on coreboot and iPXE projects to your daily life....
Categories: coreboot firmware security
Boot Guard - pre-execution firmware verification on Protectli FW6
Published at February 21, 2020 · 9 min read
This post will not describe how to guard your shoes. However, will definitely introduce you to Boot Guard feature present on Intel processors which allows firmware verification before the first instruction executes. One may call it pre-execution firmware verification. The post will also show you how Boot Guard can work well with coreboot based firmware on an example of Protectli FW6....
Meltdown and Spectre on PC Engines apu2
Published at May 29, 2019 · 9 min read
As a continuation the Meltdown and Spectre blog post, this post present the vulnerability status and mitigation with microcode update on PC Engines apu2. Read the post and get to know the open source tools for vulnerability and mitigation checks, as well as exploiting proof of concepts....
Meltdown and spectre. What are they and what they are not?
Published at March 20, 2019 · 6 min read
Meltdown and Spectre At the turn of the year 2017 and 2018, the world of security and computing has shaken. It was the time when we first heard about vulnerabilities that affect almost every modern processor (mainly x86 architecture) manufactured during the last 20 years. They have been named as Meltdown and Spectre and belong to one family of flaws caused by speculative execution. In this post, I will describe what they are and how they are threatening the users of modern machines....
Categories: security
How to enable Core Performance Boost on AMD platforms?
Published at February 14, 2019 · 13 min read
Pushing hardware to its limits In the epoch of efficient and fast processors, performance becomes one of the most crucial aspects when choosing and working with hardware. We want our computers to execute their tasks with possibly highest speeds. But what really influences the performance of our platforms? It’s the processor’s manufacturer design one may say. In this post, I will show You how firmware may boost Your silicon to higher performance level....
Categories: firmware
How to handle a DHT22 sensor using ARM mbed OS?
Published at August 1, 2017 · 8 min read
Recently I have encountered with temperature and humidity measurements using DHT22 sensor. I was developing a driver source code in ARM mbed OS SDK on particular STM32 NUCLEO L432KC platform. Thorough analysis of DHT22 documentation led me to the following questions: Is it possible to accurately measure voltage-level durations during read process? What duration time values should be considered as timeout or/and error? Should I weaken the time restrictions in order to avoid random delays in voltage level transitions be considered as failure?...